[adc_ctrl] Updates to LP -> NP transition #21829
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This is not fully clean and needs DIF/DV alignments. I just wanted to put this draft up for review to see whether these CSR changes are along the lines of what we think we need. |
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From the description, it sounds exactly as what we need. |
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msfschaffner
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hw/ip/adc_ctrl/data/adc_ctrl.hjson
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| { name: "filter_status", | |||
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@moidx @timothytrippel PTAL
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The DIF has been aligned, but the DV environment still needs patches and fails currently. |
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a-will
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Signed-off-by: Michael Schaffner <[email protected]>
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Ok the latest force push updates the block-level DV and models the new FSM behavior and the new interrupt/wakeup source, so that it is implicitly tested by randomized sequences like |
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The ADC_CTRL FSM has a low power sensing mode where ADC samples are taken at a low sampling rate. If a match is seen, it transitions to normal sampling mode in order to confirm the match. Unfortunately, if it does not confirm the match and the chip is in a low-power (sleep) state, the ADC_CTRL FSM stays in normal sampling mode and does not wake up the chip. This is not ideal from a power perspective, since in normal sampling mode, the average power consumption is much higher due to regular ADC sampling. This patch fixes that and introduces a condition in the normal sampling mode that automatically sends the FSM back to low power sampling if a match cannot be confirmed in the normal sampling mode (in case the ADC_CTRL is configured do use low power sampling). Fixes lowRISC#13725 Signed-off-by: Michael Schaffner <[email protected]>
Note that this register is automatically synced from AON to bus clock domain as part of the auto-generated reg node. Signed-off-by: Michael Schaffner <[email protected]>
Signed-off-by: Michael Schaffner <[email protected]>
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This contains the following patches:
3) in preparation for 4), the redundant filter_status register is removed as described in #11354-> this is reverted as it is not strictly required, and would change the current wakeup detection logic to get intertwined with the interrupt logic. this in turn would require a more significant DV update for which we currently do not have the resources for.